As in binary a multiple valued programmable logic array pla realises a sum ofproducts expression specified by the user however in multiple valued logic there are many more operations than in binary and an important question is the choice of operations which provides the greatest number of functions for a given chip area. The goal of this thesis is the development of a programmable logic array pla that accepts multiple valued inputs and produces multiple valued outputs the pla is implemented in cmos and multiple levels are encoded as current it is programmed by choosing transistor geometries which control the current level at which the pla reacts to inputs. The goal of this thesis is the development of a programmable logic array pla that accepts multiple valued inputs and produces multiple valued outputs the pla is implemented in cmos and multiple . Thesis advisor jon t butler available from national technical information service springfield va ada205307 thesis ms in ee naval postgraduate school dec 1988 includes bibliographical references. Design of programmable interconnect for sublithographic programmable logic arrays andre dehon dept of cs 256 80 california institute of technology pasadena ca 91125 andreacmorg abstract sublithographic programmable logic arrays can be inter connected and restored using nanoscale wires building on a hybrid of bottom up assembly
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